1. Field of the Invention
The present invention relates generally to analog-to-digital (ADC) converter input circuits, and more specifically, to an ADC input circuit with optimized power consumption versus sample rate.
2. Background of the Invention
The input circuit of a low-noise analog-to-digital converter (ADC) may consume a significant amount of the total power used by the ADC, particularly at low sample rates. The noise level at the first amplifier stage, which may be a preamplifier (buffer) or the first stage of the loop filter of a delta-sigma modulator-based ADC, typically dominates the signal-to-noise ratio (SNR). Therefore, the bias current of the first amplifier stage must be high enough so that thermal noise will not degrade the SNR. Furthermore, the bias current also must be high enough to ensure that distortion levels, e.g., the total harmonic distortion (THD), are within the required performance range. The distortion levels are dependent on both the linearity of the amplifiers, and their slew rate.
In sample rate converters supporting a wide range of sampling rates, the slew rate requirements vary. At high sampling rates, the settling time must necessarily be decreased, requiring a wider bandwidth, and consequently more power provided to the amplifier stages. Generally, the settling time and SNR demand a highest power level from the first amplifier/integrator of the loop filter, as to maximize the SNR, the gain of the first integrator stage is typically set to a high value. At lower sampling rates, the settling time can be longer, and circuits have been proposed to adjust the power level of the first integrator stage by adjusting the bias current level to save power when the settling time requirements are lower. However, power consumption of an amplifier is generally not linear with settling time, and reduction of the bias current typically leads to an increase in non-linearity. Furthermore, operation of an amplifier over a wide range of bias current leads to a wide variation in operating point, which makes design of the circuits incorporating the amplifier very complex.
In sample rate converters having a programmable gain discrete-time integrator in the first, settling time and slew rate requirements also vary, as the gain is changed by changing the input sampling capacitor, and at the maximum gain/maximum sampling capacitance value will require larger output current levels to produce the required settling time.
Therefore, it would be desirable to provide an input circuit for an ADC that uses power efficiently over a wide range of bandwidth, gain, and noise requirements for the first amplifier stage.